02111nam a2200349 a 4500 13210431 100703s2003 njua b 001 0 eng d 2003269714 9788177589184 0130449113 DLC DLC DLC DB-DhAAL 621.39/2 22 Palnitkar, Samir. Verilog HDL : a guide to digital design and synthesis / Samir Palnitkar ; [foreword by Prabhu Goel]. 2nd ed. Upper Saddle River, NJ ; New Delhi : Pearson, c2003. xlii, 450 p. : ill. ; 25 cm. + 1 CD-ROM (4 3/4 in.) "A Prentice Hall title." "Professional technical reference"--P. [4] cover. Includes bibliographical references (p. 439-440) and index. Verilog (Computer hardware description language) 9145 9145 0 0 ddc 0 0 BRACUL BRACUL GEN 2010-07-03 1 2 621.392 PAL 3010020572 2022-06-13 2022-05-18 1 2010-07-03 BK 0 0 ddc 0 0 BRACUL BRACUL GEN 2010-07-03 3 10 621.392 PAL 3010020573 2025-08-04 2025-07-02 2 2010-07-03 BK 0 0 ddc 0 0 BRACUL BRACUL GEN 2010-07-03 2 20 621.392 PAL 3010020574 2025-10-21 2025-07-24 3 2010-07-03 BK 0 0 ddc 0 0 BRACUL BRACUL GEN 2010-07-03 3 25 621.392 PAL 3010020575 2025-09-18 2025-06-26 4 2010-07-03 BK 0 0 ddc 0 0 BRACUL BRACUL AV 2010-07-03 0 621.392 PAL 4010020572 2010-07-03 1 2010-07-03 AV 0 0 ddc 0 0 BRACUL BRACUL AV 2010-07-03 0 621.392 PAL 4010020573 2010-07-03 2 2010-07-03 AV 0 0 ddc 0 0 BRACUL BRACUL AV 2010-07-03 0 621.392 PAL 4010020574 2010-07-03 3 2010-07-03 AV 0 0 ddc 0 0 BRACUL BRACUL AV 2010-07-03 0 621.392 PAL 4010020575 2010-07-03 4 2010-07-03 AV