APA (7th ed.) Citation

Vaidyanathan, K. (2016). Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling. SPIE. https://doi.org/10.1117/3.2217861

Chicago Style (17th ed.) Citation

Vaidyanathan, Kaushik. Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling. SPIE, 2016. https://doi.org/10.1117/3.2217861.

MLA (8th ed.) Citation

Vaidyanathan, Kaushik. Design Technology Co-Optimization in the Era of Sub-Resolution IC Scaling. SPIE, 2016. https://doi.org/10.1117/3.2217861.

Warning: These citations may not always be 100% accurate.